CPU_ENABLE_SSE changed to CPU_DISABLE_SSE

[Craig Dooley <cd5697@xxxxxxxxxx>]

New default is to include SSE support unless explicitly told otherwise.  This 
should help a couple multimedia ports like mplayer.  
-- 
Craig Dooley						 cd5697@xxxxxxxxxx

Index: conf/options.i386
===================================================================
RCS file: /home/dcvs/src/sys/conf/options.i386,v
retrieving revision 1.2
diff -u -r1.2 options.i386
--- conf/options.i386	17 Jun 2003 04:28:20 -0000	1.2
+++ conf/options.i386	29 Jul 2003 12:58:07 -0000
@@ -65,7 +65,7 @@
 CYRIX_CACHE_WORKS		opt_cpu.h
 CYRIX_CACHE_REALLY_WORKS	opt_cpu.h
 NO_MEMORY_HOLE			opt_cpu.h
-CPU_ENABLE_SSE			opt_cpu.h
+CPU_DISABLE_SSE			opt_cpu.h
 CPU_ATHLON_SSE_HACK		opt_cpu.h
 
 # The CPU type affects the endian conversion functions all over the kernel.
Index: conf/options.pc98
===================================================================
RCS file: /home/dcvs/src/sys/conf/options.pc98,v
retrieving revision 1.2
diff -u -r1.2 options.pc98
--- conf/options.pc98	17 Jun 2003 04:28:20 -0000	1.2
+++ conf/options.pc98	29 Jul 2003 13:00:12 -0000
@@ -64,7 +64,7 @@
 CYRIX_CACHE_WORKS		opt_cpu.h
 CYRIX_CACHE_REALLY_WORKS	opt_cpu.h
 NO_MEMORY_HOLE			opt_cpu.h
-CPU_ENABLE_SSE			opt_cpu.h
+CPU_DISABLE_SSE			opt_cpu.h
 CPU_ATHLON_SSE_HACK		opt_cpu.h
 
 # The CPU type affects the endian conversion functions all over the kernel.
Index: i386/conf/LINT
===================================================================
RCS file: /home/dcvs/src/sys/i386/conf/LINT,v
retrieving revision 1.2
diff -u -r1.2 LINT
--- i386/conf/LINT	17 Jun 2003 04:28:35 -0000	1.2
+++ i386/conf/LINT	29 Jul 2003 13:01:17 -0000
@@ -177,7 +177,7 @@
 # reorder).  This option should not be used if you use memory mapped
 # I/O device(s).
 #
-# CPU_ENABLE_SSE enables SSE/MMX2 instructions support.
+# CPU_DISABLE_SSE disables SSE/MMX2 instructions support.
 #
 # CPU_FASTER_5X86_FPU enables faster FPU exception handler.
 #
@@ -244,7 +244,7 @@
 options 	CPU_DIRECT_MAPPED_CACHE
 options 	CPU_DISABLE_5X86_LSSER
 options 	CPU_ELAN
-options 	CPU_ENABLE_SSE
+options 	CPU_DISABLE_SSE
 options 	CPU_FASTER_5X86_FPU
 options 	CPU_I486_ON_386
 options 	CPU_IORT
Index: i386/i386/initcpu.c
===================================================================
RCS file: /home/dcvs/src/sys/i386/i386/initcpu.c,v
retrieving revision 1.4
diff -u -r1.4 initcpu.c
--- i386/i386/initcpu.c	21 Jul 2003 07:57:43 -0000	1.4
+++ i386/i386/initcpu.c	29 Jul 2003 13:12:53 -0000
@@ -69,7 +69,7 @@
 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
     &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
 
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 u_int	cpu_fxsr;		/* SSE enabled */
 #endif
 
@@ -519,8 +519,8 @@
 void
 enable_sse(void)
 {
-#if defined(CPU_ENABLE_SSE)
-	if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
+#ifndef(CPU_DISABLE_SSE)
+	if ((cpu_feature & CPUID_SSE) && (cpu_feature & CPUID_FXSR)) {
 		load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
 		cpu_fxsr = hw_instruction_sse = 1;
 	}
Index: i386/i386/machdep.c
===================================================================
RCS file: /home/dcvs/src/sys/i386/i386/machdep.c,v
retrieving revision 1.30
diff -u -r1.30 machdep.c
--- i386/i386/machdep.c	26 Jul 2003 19:07:47 -0000	1.30
+++ i386/i386/machdep.c	29 Jul 2003 13:05:38 -0000
@@ -128,10 +128,10 @@
 extern void initializecpu(void);
 
 static void cpu_startup __P((void *));
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 static void set_fpregs_xmm __P((struct save87 *, struct savexmm *));
 static void fill_fpregs_xmm __P((struct savexmm *, struct save87 *));
-#endif /* CPU_ENABLE_SSE */
+#endif /* CPU_DISABLE_SSE */
 #ifdef DIRECTIO
 extern void ffs_rawread_setup(void);
 #endif /* DIRECTIO */
@@ -2263,7 +2263,7 @@
 	return (0);
 }
 
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 static void
 fill_fpregs_xmm(sv_xmm, sv_87)
 	struct savexmm *sv_xmm;
@@ -2315,20 +2315,20 @@
 
 	sv_xmm->sv_ex_sw = sv_87->sv_ex_sw;
 }
-#endif /* CPU_ENABLE_SSE */
+#endif /* CPU_DISABLE_SSE */
 
 int
 fill_fpregs(p, fpregs)
 	struct proc *p;
 	struct fpreg *fpregs;
 {
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 	if (cpu_fxsr) {
 		fill_fpregs_xmm(&p->p_thread->td_pcb->pcb_save.sv_xmm,
 						(struct save87 *)fpregs);
 		return (0);
 	}
-#endif /* CPU_ENABLE_SSE */
+#endif /* CPU_DISABLE_SSE */
 	bcopy(&p->p_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
 	return (0);
 }
@@ -2338,13 +2338,13 @@
 	struct proc *p;
 	struct fpreg *fpregs;
 {
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 	if (cpu_fxsr) {
 		set_fpregs_xmm((struct save87 *)fpregs,
 				       &p->p_thread->td_pcb->pcb_save.sv_xmm);
 		return (0);
 	}
-#endif /* CPU_ENABLE_SSE */
+#endif /* CPU_DISABLE_SSE */
 	bcopy(fpregs, &p->p_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
 	return (0);
 }
Index: i386/isa/npx.c
===================================================================
RCS file: /home/dcvs/src/sys/i386/isa/npx.c,v
retrieving revision 1.10
diff -u -r1.10 npx.c
--- i386/isa/npx.c	23 Jul 2003 02:30:19 -0000	1.10
+++ i386/isa/npx.c	29 Jul 2003 13:08:24 -0000
@@ -99,7 +99,7 @@
 #define	fnstsw(addr)		__asm __volatile("fnstsw %0" : "=m" (*(addr)))
 #define	fp_divide_by_0()	__asm("fldz; fld1; fdiv %st,%st(1); fnop")
 #define	frstor(addr)		__asm("frstor %0" : : "m" (*(addr)))
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 #define	fxrstor(addr)		__asm("fxrstor %0" : : "m" (*(addr)))
 #define	fxsave(addr)		__asm __volatile("fxsave %0" : "=m" (*(addr)))
 #endif
@@ -118,7 +118,7 @@
 void	fnstsw		__P((caddr_t addr));
 void	fp_divide_by_0	__P((void));
 void	frstor		__P((caddr_t addr));
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 void	fxsave		__P((caddr_t addr));
 void	fxrstor		__P((caddr_t addr));
 #endif
@@ -127,15 +127,15 @@
 
 #endif	/* __GNUC__ */
 
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 #define GET_FPU_EXSW_PTR(pcb) \
 	(cpu_fxsr ? \
 		&(pcb)->pcb_save.sv_xmm.sv_ex_sw : \
 		&(pcb)->pcb_save.sv_87.sv_ex_sw)
-#else /* CPU_ENABLE_SSE */
+#else /* CPU_DISABLE_SSE */
 #define GET_FPU_EXSW_PTR(pcb) \
 	(&(pcb)->pcb_save.sv_87.sv_ex_sw)
-#endif /* CPU_ENABLE_SSE */
+#endif /* CPU_DISABLE_SSE */
 
 typedef u_char bool_t;
 
@@ -508,7 +508,7 @@
 	 */
 	npxsave(&dummy);
 	stop_emulating();
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 	/* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */
 	if (cpu_fxsr)
 		fninit();
@@ -871,7 +871,7 @@
 npxsave(addr)
 	union savefpu *addr;
 {
-#if defined(SMP) || defined(CPU_ENABLE_SSE)
+#if defined(SMP) || !defined(CPU_DISABLE_SSE)
 
 	stop_emulating();
 	fpusave(addr);
@@ -880,7 +880,7 @@
 	start_emulating();
 	mdcpu->gd_npxthread = NULL;
 
-#else /* SMP or CPU_ENABLE_SSE */
+#else /* SMP or !CPU_DISABLE_SSE */
 
 	u_char	icu1_mask;
 	u_char	icu2_mask;
@@ -922,7 +922,7 @@
       union savefpu *addr;
 {
 
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 	if (cpu_fxsr)
 		fxsave(addr);
 	else
@@ -935,7 +935,7 @@
       union savefpu *addr;
 {
 
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 	if (cpu_fxsr)
 		fxrstor(addr);
 	else
Index: i386/linux/linux_ptrace.c
===================================================================
RCS file: /home/dcvs/src/sys/i386/linux/linux_ptrace.c,v
retrieving revision 1.5
diff -u -r1.5 linux_ptrace.c
--- i386/linux/linux_ptrace.c	26 Jul 2003 18:12:43 -0000	1.5
+++ i386/linux/linux_ptrace.c	29 Jul 2003 13:09:44 -0000
@@ -215,7 +215,7 @@
 	l_long		padding[56];
 };
 
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 static int
 linux_proc_read_fpxregs(struct proc *p, struct linux_pt_fpxreg *fpxregs)
 {
@@ -339,7 +339,7 @@
 		}
 		break;
 	case PTRACE_SETFPXREGS:
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 		error = copyin((caddr_t)uap->data, &r.fpxreg,
 		    sizeof(r.fpxreg));
 		if (error)
@@ -347,7 +347,7 @@
 #endif
 		/* FALL THROUGH */
 	case PTRACE_GETFPXREGS: {
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 		struct proc *p;
 
 		if (sizeof(struct linux_pt_fpxreg) != sizeof(struct savexmm)) {
Index: pc98/i386/machdep.c
===================================================================
RCS file: /home/dcvs/src/sys/pc98/i386/machdep.c,v
retrieving revision 1.6
diff -u -r1.6 machdep.c
--- pc98/i386/machdep.c	26 Jul 2003 21:35:27 -0000	1.6
+++ pc98/i386/machdep.c	29 Jul 2003 13:10:24 -0000
@@ -133,10 +133,10 @@
 extern void initializecpu(void);
 
 static void cpu_startup __P((void *));
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 static void set_fpregs_xmm __P((struct save87 *, struct savexmm *));
 static void fill_fpregs_xmm __P((struct savexmm *, struct save87 *));
-#endif /* CPU_ENABLE_SSE */
+#endif /* CPU_DISABLE_SSE */
 #ifdef DIRECTIO
 extern void ffs_rawread_setup(void);
 #endif /* DIRECTIO */
@@ -2293,7 +2293,7 @@
 	return (0);
 }
 
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 static void
 fill_fpregs_xmm(sv_xmm, sv_87)
 	struct savexmm *sv_xmm;
@@ -2345,20 +2345,20 @@
 
 	sv_xmm->sv_ex_sw = sv_87->sv_ex_sw;
 }
-#endif /* CPU_ENABLE_SSE */
+#endif /* CPU_DISABLE_SSE */
 
 int
 fill_fpregs(p, fpregs)
 	struct proc *p;
 	struct fpreg *fpregs;
 {
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 	if (cpu_fxsr) {
 		fill_fpregs_xmm(&p->p_addr->u_pcb.pcb_save.sv_xmm,
 						(struct save87 *)fpregs);
 		return (0);
 	}
-#endif /* CPU_ENABLE_SSE */
+#endif /* CPU_DISABLE_SSE */
 	bcopy(&p->p_addr->u_pcb.pcb_save.sv_87, fpregs, sizeof *fpregs);
 	return (0);
 }
@@ -2368,13 +2368,13 @@
 	struct proc *p;
 	struct fpreg *fpregs;
 {
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 	if (cpu_fxsr) {
 		set_fpregs_xmm((struct save87 *)fpregs,
 					   &p->p_addr->u_pcb.pcb_save.sv_xmm);
 		return (0);
 	}
-#endif /* CPU_ENABLE_SSE */
+#endif /* CPU_DISABLE_SSE */
 	bcopy(fpregs, &p->p_addr->u_pcb.pcb_save.sv_87, sizeof *fpregs);
 	return (0);
 }
Index: pc98/pc98/npx.c
===================================================================
RCS file: /home/dcvs/src/sys/pc98/pc98/npx.c,v
retrieving revision 1.4
diff -u -r1.4 npx.c
--- pc98/pc98/npx.c	10 Jul 2003 04:47:55 -0000	1.4
+++ pc98/pc98/npx.c	29 Jul 2003 13:11:19 -0000
@@ -103,7 +103,7 @@
 #define	fnstsw(addr)		__asm __volatile("fnstsw %0" : "=m" (*(addr)))
 #define	fp_divide_by_0()	__asm("fldz; fld1; fdiv %st,%st(1); fnop")
 #define	frstor(addr)		__asm("frstor %0" : : "m" (*(addr)))
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 #define	fxrstor(addr)		__asm("fxrstor %0" : : "m" (*(addr)))
 #define	fxsave(addr)		__asm __volatile("fxsave %0" : "=m" (*(addr)))
 #endif
@@ -122,7 +122,7 @@
 void	fnstsw		__P((caddr_t addr));
 void	fp_divide_by_0	__P((void));
 void	frstor		__P((caddr_t addr));
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 void	fxsave		__P((caddr_t addr));
 void	fxrstor		__P((caddr_t addr));
 #endif
@@ -131,15 +131,15 @@
 
 #endif	/* __GNUC__ */
 
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 #define GET_FPU_EXSW_PTR(pcb) \
 	(cpu_fxsr ? \
 		&(pcb)->pcb_save.sv_xmm.sv_ex_sw : \
 		&(pcb)->pcb_save.sv_87.sv_ex_sw)
-#else /* CPU_ENABLE_SSE */
+#else /* CPU_DISABLE_SSE */
 #define GET_FPU_EXSW_PTR(pcb) \
 	(&(pcb)->pcb_save.sv_87.sv_ex_sw)
-#endif /* CPU_ENABLE_SSE */
+#endif /* CPU_DISABLE_SSE */
 
 typedef u_char bool_t;
 
@@ -557,7 +557,7 @@
 	 */
 	npxsave(&dummy);
 	stop_emulating();
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 	/* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */
 	if (cpu_fxsr)
 		fninit();
@@ -912,7 +912,7 @@
 npxsave(addr)
 	union savefpu *addr;
 {
-#if defined(SMP) || defined(CPU_ENABLE_SSE)
+#if defined(SMP) || !defined(CPU_DISABLE_SSE)
 
 	stop_emulating();
 	fpusave(addr);
@@ -921,7 +921,7 @@
 	start_emulating();
 	mdcpu->gd_npxthread = NULL;
 
-#else /* SMP or CPU_ENABLE_SSE */
+#else /* SMP or CPU_DISABLE_SSE */
 
 	u_char	icu1_mask;
 	u_char	icu2_mask;
@@ -981,7 +981,7 @@
       union savefpu *addr;
 {
 
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 	if (cpu_fxsr)
 		fxsave(addr);
 	else
@@ -994,7 +994,7 @@
       union savefpu *addr;
 {
 
-#ifdef CPU_ENABLE_SSE
+#ifndef CPU_DISABLE_SSE
 	if (cpu_fxsr)
 		fxrstor(addr);
 	else