DragonFly kernel List (threaded) for 2007-06
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Re: Decision time.... should NATA become the default for this release?
1D31E.6030805@online.de> <200706022051.l52Kp9IY038754@apollo.backplane.com>
In-Reply-To: <200706022051.l52Kp9IY038754@apollo.backplane.com>
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Matthew Dillon wrote:
> :Nope, sorry. Still the same result (rcorder segfaults etc.).
> :
> :Sascha
> :
> :--
> :http://yoyodyne.ath.cx
>
> It's got to be reg48, reg4a, or reg54.
>
> Try this patch. Note that its relative /usr/src/sys/dev/disk. I added
> printf's to both ATA and NATA, please tell me what the output says for
> both the NATA and ATA kernels.
>
> I also changed another pci_write_config, so it might magically work
> (tell me if it does or doesn't).
The patch contains the ata-chipset.c part twice (as nata/ata-chipset.c
and as ata-chipset.c). After removing the last one, it applied cleanly
from sys/dev/disk.
But it still doesn't work. :(
NATA output:
. ..
ad0: setting PIO4 on PIIX4 chip
ad0: regs before 40=e303e307 44=00 48=05 4a=0202 54=0000
ad0: regs after 40=e377e377 44=00 48=04 4a=0200 54=0000
ad0: setting UDMA33 on PIIX4 chip
ad0: regs before 40=e377e377 44=00 48=04 4a=0200 54=0000
ad0: regs after 40=e377e377 44=00 48=05 4a=0201 54=0000
. ..
acd0: setting PIO4 on PIIX4 chip
acd0: regs before 40=e377e377 44=00 48=05 4a=0201 54=0000
acd0: regs after 40=e377e377 44=00 48=01 4a=0001 54=0000
acd0: setting UDMA33 on PIIX4 chip
acd0: regs before 40=e377e377 44=00 48=01 4a=0001 54=0000
acd0: regs after 40=e377e377 44=00 48=05 4a=0101 54=0000
. ..
ATA output:
. ..
ad0: success setting UDMA2 on Intel chip
ata0: regs after 40=e303e307 44=00 48=05 4a=0202 54=0000
. ..
Sascha
--
http://yoyodyne.ath.cx
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