Re: Decision time.... should NATA become the default for this release?

[Matthew Dillon <dillon@xxxxxxxxxxxxxxxxxxxx>]

:OK, relevant lines from NATA and ATA follow.

    Ok.  Hmm.  It looks ok.

    (1) Is your ATA device on the PCI bus or is it a legacy ISA device?
	Do a normal ATA boot and run pciconf -l.

	I'm a bit worried that it just stopped working entirely with the most
	recent update to HEAD.  The Intel chipinit code basically didn't
	change at all.

    (2) Please try this patch.  I noticed that some bits in reg54
	were being improperly overwritten for UDMA2 mode.  If you look
	at the original code, the clause for UDMA5 overwrites the
	bits that were set or cleared for UDMA2.

						-Matt

Index: ata-chipset.c
===================================================================
RCS file: /cvs/src/sys/dev/disk/nata/ata-chipset.c,v
retrieving revision 1.4
diff -u -r1.4 ata-chipset.c
--- ata-chipset.c	1 Jun 2007 00:31:14 -0000	1.4
+++ ata-chipset.c	2 Jun 2007 19:31:03 -0000
@@ -1891,16 +1891,21 @@
 	pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);
 	pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))), 2);
     }
+
+    /*
+     * reg54
+     */
     reg54 |= 0x0400;
     if (mode >= ATA_UDMA2)
-	pci_write_config(gparent, 0x54, reg54 | (0x1 << devno), 2);
+	reg54 |= (0x1 << devno);
     else
-	pci_write_config(gparent, 0x54, reg54 & ~(0x1 << devno), 2);
+	reg54 &= ~(0x1 << devno);
 
     if (mode >= ATA_UDMA5)
-	pci_write_config(gparent, 0x54, reg54 | (0x1000 << devno), 2);
+	reg54 |= (0x1000 << devno);
     else 
-	pci_write_config(gparent, 0x54, reg54 & ~(0x1000 << devno), 2);
+	reg54 &= ~(0x1000 << devno);
+    pci_write_config(gparent, 0x54, reg54, 2);
 
     reg40 &= ~0x00ff00ff;
     reg40 |= 0x40774077;