cvs commit: src/sys/dev/disk/aic7xxx aic79xx.c aic79xx.h aic79xx.reg aic79xx.seq aic79xx_inline.h aic79xx_osm.c aic79xx_pci.c

[Peter Avalos <pavalos@xxxxxxxxxxxxxxxxxxxxxxx>]

pavalos     2007/07/05 19:40:58 PDT

DragonFly src repository

  Modified files:
    sys/dev/disk/aic7xxx aic79xx.c aic79xx.h aic79xx.reg 
                         aic79xx.seq aic79xx_inline.h 
                         aic79xx_osm.c aic79xx_pci.c 
  Log:
  Correct a very rare case where command ordering could be compromised
  by a transaction performing a driver handled message sequence (an
  scb with the MK_MESSAGE flag set).
  
  SCBs that perform host managed messaging must always be
  at the head of their per-target selection queue so that
  the firmware knows to manually assert ATN if the current
  negotiation agreement is packetized.  In the past we
  guaranteed this by queuing these SCBs separarately in
  the execution queue.  This exposes the system to potential
  command reordering in two cases:
  
  1) Another SCB for the same ITL nexus is queued that does
     not have the MK_MESSAGE flag set.  This SCB will be
     queued to the per-target list which can be serviced
     before the MK_MESSAGE scb that preceeded it.
  
  2) If the target cannot accept all of the commands in the
     per-target selection queue in one selection, the remainder
     is queued to the tail of the selection queues so as to
     effect round-robin scheduling.  This could allow the
     MK_MESSAGE scb to be sent to the target before the
     requeued commands.
  
  This commit changes the firmware policy to defer queuing
  MK_MESSAGE SCBs into the selection queues until this can
  be done without affecting order.  This means that the
  target's selection queue is either empty, or the last
  SCB on the execution queue is also a MK_MESSAGE SCB.
  During any wait, the firmware halts the download of new
  SCBs so only a single "holding location" is required.
  
  Luckily, MK_MESSAGE SCBs are rare and typically occur only
  during CAM's bus probe where only one command is outstanding
  at a time.  However, during some recovery scenarios, the
  reordering *could* occur.
  
  aic79xx.c:
  	Update ahd_search_qinfifo() and helper routines to
  	search for pending MK_MESSAGE scbs and properly
  	restitch the execution queue if either the MK_MESSAGE
  	SCB is being aborted, or the MK_MESSAGE SCB can be
  	queued due to the execution queue draining due to
  	aborts.
  
  	Enable LQOBUSFREE status to assert an interrupt.
  	This should be redundant since a BUSFREE interrupt
  	should always occur along with an LQOBUSFREE event,
  	but on the Rev A, this doesn't seem to be guaranteed.
  
  	When a PPR request is rejected when a previously
  	existing packetized agreement is in place, assume
  	that the target has been reset without our knowledge
  	and revert to async/narrow transfers.  This corrects
  	two issues: the stale ENATNO setting that was used
  	to send the PPR is cleared so the firmware is not
  	confused by a future packetized selection with
  	ATN asserted but no MK_MESSAGE flag in the SCB and
  	it speeds up recovery by aborting any pending
  	packetized transactions that by definition are now
  	dead.
  
  	When re-queueing SCBs after a failed negotiation
  	attempt, ensure command ordering by freezing the
  	device queue first.
  
  	Traverse the list of pending SCBs rather than the
  	whole SCB array on the controller when pushing
  	MK_MESSAGE flag changes out to the controller.
  	The original code was optimized for the aic7xxx
  	controllers where there are fewer controller slots
  	then pending SCBs and the firmware picks SCB
  	slots.  For the U320 controller, the hope is
  	that we have fewer pending SCBs then the 512
  	slots on the controller.
  
  	Enhance some diagnostics.
  
  	Factor out some common code.
  
  aic79xx.h:
  	Add prototype for new ahd_done_with_status() that is
  	used to factor out some commone code.
  
  aic79xx.reg:
  	Add definisions for the pending MK_MESSAGE SCB.
  
  aic79xx.seq:
  	Defer MK_MESSAGE SCB queing to the execution queue
  	so as to preserve command ordering.  Re-arrange some
  	of the selection processing code so the above change
  	had no performance impact on the common code path.
  
  	Close a few critical section holes.
  
  	When entering a non-packetized phase, manually enable
  	busfree interrupts, since the controller hardware
  	does not do this automatically.
  
  aic79xx_inline.h:
  	Enhance logging for queued SCBs.
  
  aic79xx_osm.c:
  	Add new a new DDB ahd command, ahd_dump, which
  	invokes the ahd_dump_card_state() routine on the
  	unit specified with the ahd_sunit DDB command.
  
  aic79xx_pci.c:
  	Turn on the BUSFREEREV bug for the Rev B. controller.
  	This is required to close the busfree during non-packetized
  	phase hole.
  
  Obtained-from: FreeBSD
  
  Revision  Changes    Path
  1.21      +194 -77   src/sys/dev/disk/aic7xxx/aic79xx.c
  1.9       +3 -1      src/sys/dev/disk/aic7xxx/aic79xx.h
  1.5       +25 -4     src/sys/dev/disk/aic7xxx/aic79xx.reg
  1.8       +120 -23   src/sys/dev/disk/aic7xxx/aic79xx.seq
  1.8       +4 -3      src/sys/dev/disk/aic7xxx/aic79xx_inline.h
  1.16      +16 -7     src/sys/dev/disk/aic7xxx/aic79xx_osm.c
  1.12      +3 -2      src/sys/dev/disk/aic7xxx/aic79xx_pci.c


http://www.dragonflybsd.org/cvsweb/src/sys/dev/disk/aic7xxx/aic79xx.c.diff?r1=1.20&r2=1.21&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/dev/disk/aic7xxx/aic79xx.h.diff?r1=1.8&r2=1.9&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/dev/disk/aic7xxx/aic79xx.reg.diff?r1=1.4&r2=1.5&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/dev/disk/aic7xxx/aic79xx.seq.diff?r1=1.7&r2=1.8&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/dev/disk/aic7xxx/aic79xx_inline.h.diff?r1=1.7&r2=1.8&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/dev/disk/aic7xxx/aic79xx_osm.c.diff?r1=1.15&r2=1.16&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/dev/disk/aic7xxx/aic79xx_pci.c.diff?r1=1.11&r2=1.12&f=u