cvs commit: src/sys/dev/disk/aic7xxx aic79xx.c aic79xx.h aic79xx.reg aic79xx.seq aic79xx_inline.h aic79xx_pci.c

[Peter Avalos <pavalos@xxxxxxxxxxxxxxxxxxxxxxx>]

pavalos     2007/07/05 19:23:32 PDT

DragonFly src repository

  Modified files:
    sys/dev/disk/aic7xxx aic79xx.c aic79xx.h aic79xx.reg 
                         aic79xx.seq aic79xx_inline.h 
                         aic79xx_pci.c 
  Log:
  aic79xx.c:
  	Allow 500us between pauses in ahd_pause_and_flushwork().
  	The maximum we will wait is now 500ms.
  
  	In the same routine, remove any attempt to clear ENSELO.
  	Let the firmware do it once the current selection has
  	completed.  This avoids some race conditions having to
  	do with non-packetized completions and the auto-clearing
  	of ENSELO on packetized completions.
  
  	Also avoid attempts to clear critical sections when
  	interrups are pending.  We are going to loop again
  	anyway, so clearing critical sections is a waste of
  	time.  It also may not be possible to clear a critical
  	section if the source of the interrupt was a SEQINT.
  
  aic79xx_pci.c:
  	Use the Generic 9005 mask when looking for generic 7901B
  	parts.  This allows the driver to attach to 7901B parts
  	on motherboards using a non-Adaptec subvendor ID.
  
  aic79xx_inline.h:
  	Test for the SCBRAM_RD_BUG against the bugs
  	field, not the flags field in the softc.
  
  aic79xx.c:
  	Cancel pending transactions on devices that
  	respond with a selection timeout.  This decreases
  	the duration of timeout recovery when a device
  	disappears.
  
  aic79xx.c:
  	Don't bother forcing renegotiation on a selection
  	timeout now that we use the device reset handler
  	to abort any pending commands on the target.
  	The device reset handler already takes us down
  	to async narrow and forces a renegotiation.
  
  	In the device reset handlers, only send a
  	BDR sent async event if the status is not
  	CAM_SEL_TIMEOUT.  This avoids sending this
  	event in the selection timeout case
  
  aic79xx.c:
  	Modify the Core timeout handler to verify that another
  	command has the potential to timeout before passing off
  	a command timeout as due to some other command.  This
  	safety measure is added in response to a timeout recovery
  	failure on H2B where it appears that incoming reselection
  	status was lost during a drive pull test.  In that case,
  	the recovery handler continued to wait for the command
  	that was active on the bus indefinetly.  While the root
  	cause of the above issue is still being determined seems
  	a prudent safeguard.
  
  aic79xx_pci.c:
  	Add a specific probe entry for the Dell OEM 39320(B).
  
  aic79xx.c:
  aic79xx.h:
  aic79xx.reg:
  aic79xx.seq:
  	Modify the aic79xx firmware to never cross a cacheline or
  	ADB boundary when DMA'ing completion entries to the host.
  	In PCI mode, at least in 32/33 configurations, the SCB
  	DMA engine may lose its place in the data-stream should
  	the target force a retry on something other than an
  	8byte aligned boundary. In PCI-X mode, we do this to
  	avoid split transactions since many chipsets seem to be
  	unable to format proper split completions to continue
  	the data transfer.
  
  	The above change allows us to drop our completion entries
  	from 8 bytes to 4.  We were using 8 byte entries to ensure
  	that PCI retries could only occur on an 8byte aligned
  	boundary.  Now that the sequencer guarantees this by splitting
  	up completions, we can safely drop the size to 4 bytes (2
  	byte tag, one byte SG_RESID, one byte pad).
  
  	Both the split-completion and PCI retry problems only show
  	up under high tag load when interrupt coalescing is being
  	especially effective.  The switch from a 2byte completion
  	entry to an 8 byte entry to solve the PCI problem increased
  	the chance of incurring a split in PCI-X mode when multiple
  	transactions were completed at once.  Dropping the completion
  	size to 4 bytes also means that we can complete more commands
  	in a single DMA (128byte FIFO -> 32 commands instead of 16).
  
  aic79xx.c:
  	Modify the SCSIINT handler to defer clearing
  	sequencer critical sections to the individual
  	interrupt handlers.  This allows us to
  	immediately disable any outgoing selections in
  	the case of an unexpected busfree so we don't
  	inadvertantly clear ENSELO *after* a new selection
  	has started.  Doing so may cause the sequencer
  	to miss a successful selection.
  
  	In ahd_update_pending_scbs(), only clear ENSELO if
  	the bus is currently busy and a selection is not
  	already in progress or the sequencer has yet to
  	handle a pending selection.  While we want to ensure
  	that the selection for the SCB at the head of the
  	selection queue is restarted so that any change in
  	negotiation request can take effect, we can't clobber
  	pending selection state without confusing the sequencer
  	into missing a selection.
  
  Obtained-from: FreeBSD
  
  Revision  Changes    Path
  1.20      +126 -67   src/sys/dev/disk/aic7xxx/aic79xx.c
  1.8       +2 -3      src/sys/dev/disk/aic7xxx/aic79xx.h
  1.4       +3 -2      src/sys/dev/disk/aic7xxx/aic79xx.reg
  1.7       +15 -3     src/sys/dev/disk/aic7xxx/aic79xx.seq
  1.7       +3 -3      src/sys/dev/disk/aic7xxx/aic79xx_inline.h
  1.11      +10 -3     src/sys/dev/disk/aic7xxx/aic79xx_pci.c


http://www.dragonflybsd.org/cvsweb/src/sys/dev/disk/aic7xxx/aic79xx.c.diff?r1=1.19&r2=1.20&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/dev/disk/aic7xxx/aic79xx.h.diff?r1=1.7&r2=1.8&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/dev/disk/aic7xxx/aic79xx.reg.diff?r1=1.3&r2=1.4&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/dev/disk/aic7xxx/aic79xx.seq.diff?r1=1.6&r2=1.7&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/dev/disk/aic7xxx/aic79xx_inline.h.diff?r1=1.6&r2=1.7&f=u
http://www.dragonflybsd.org/cvsweb/src/sys/dev/disk/aic7xxx/aic79xx_pci.c.diff?r1=1.10&r2=1.11&f=u