DragonFly submit List (threaded) for 2004-01
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DRM updates
This is a first patch to start bringing drm in from recent cvs. This patch
enables MTRR support, and changes a few structures to get us closer. It
doesnt do much, but just turning on MTRR support got me an extra 30 fps in
glxgears (850 -> 880).
-Craig
--
------------------------------------------------------------------------
Craig Dooley craig@xxxxxxxxxx
------------------------------------------------------------------------
Index: sys/dev/drm/drm_os_freebsd.h
===================================================================
RCS file: /home/dcvs/src/sys/dev/drm/drm_os_freebsd.h,v
retrieving revision 1.7
diff -u -r1.7 drm_os_freebsd.h
--- sys/dev/drm/drm_os_freebsd.h 7 Aug 2003 21:16:55 -0000 1.7
+++ sys/dev/drm/drm_os_freebsd.h 13 Jan 2004 18:32:59 -0000
@@ -28,13 +28,17 @@
#include <machine/pmap.h>
#include <machine/bus.h>
#include <machine/resource.h>
+#if __FreeBSD_version >= 480000
+#include <sys/endian.h>
+#endif
#include <sys/mman.h>
#include <sys/rman.h>
#include <sys/memrange.h>
-#include <bus/pci/pcivar.h>
#if __FreeBSD_version >= 500000
+#include <dev/pci/pcivar.h>
#include <sys/selinfo.h>
#else
+#include <bus/pci/pcivar.h>
#include <sys/select.h>
#endif
#include <sys/bus.h>
@@ -50,10 +54,11 @@
#endif
#ifdef __i386__
-#define __REALLY_HAVE_MTRR (__HAVE_MTRR) && (__FreeBSD_version >= 500000)
+#define __REALLY_HAVE_MTRR (__HAVE_MTRR) && (__FreeBSD_version >= 460000)
#else
#define __REALLY_HAVE_MTRR 0
#endif
+
#define __REALLY_HAVE_SG (__HAVE_SG)
#if __REALLY_HAVE_AGP
@@ -99,7 +104,10 @@
#define DRM_SPINUNINIT(l)
#define DRM_SPINLOCK(l) lwkt_gettoken(l)
#define DRM_SPINUNLOCK(u) lwkt_reltoken(u);
+#define DRM_SPINLOCK_ASSERT(l)
#define DRM_CURRENTPID curthread->td_proc->p_pid
+#define DRM_LOCK lockmgr(&dev->dev_lock, LK_EXCLUSIVE, 0, DRM_CURPROC)
+#define DRM_UNLOCK lockmgr(&dev->dev_lock, LK_RELEASE, 0, DRM_CURPROC)
#endif
/* Currently our DRMFILE (filp) is a void * which is actually the pid
@@ -107,11 +115,12 @@
* code for that is not yet written */
#define DRMFILE void *
#define DRM_IOCTL_ARGS dev_t kdev, u_long cmd, caddr_t data, int flags, DRM_STRUCTPROC *p, DRMFILE filp
-#define DRM_LOCK lockmgr(&dev->dev_lock, LK_EXCLUSIVE, 0, DRM_CURPROC)
-#define DRM_UNLOCK lockmgr(&dev->dev_lock, LK_RELEASE, 0, DRM_CURPROC)
-#define DRM_SUSER(td) suser(td)
+#define DRM_SUSER(p) suser(p)
#define DRM_TASKQUEUE_ARGS void *arg, int pending
#define DRM_IRQ_ARGS void *arg
+typedef void irqreturn_t;
+#define IRQ_HANDLED /* nothing */
+#define IRQ_NONE /* nothing */
#define DRM_DEVICE drm_device_t *dev = kdev->si_drv1
#define DRM_MALLOC(size) malloc( size, DRM(M_DRM), M_NOWAIT )
#define DRM_FREE(pt,size) free( pt, DRM(M_DRM) )
@@ -131,6 +140,23 @@
#define DRM_AGP_FIND_DEVICE() agp_find_device()
#define DRM_ERR(v) v
+#define DRM_MTRR_WC MDF_WRITECOMBINE
+
+#define DRM_GET_PRIV_WITH_RETURN(_priv, _filp) \
+do { \
+ if (_filp != (DRMFILE)DRM_CURRENTPID) { \
+ DRM_ERROR("filp doesn't match curproc\n"); \
+ return EINVAL; \
+ } \
+ DRM_LOCK(); \
+ _priv = DRM(find_file_by_proc)(dev, DRM_CURPROC); \
+ DRM_UNLOCK(); \
+ if (_priv == NULL) { \
+ DRM_DEBUG("can't find authenticator\n"); \
+ return EINVAL; \
+ } \
+} while (0)
+
#define DRM_PRIV \
drm_file_t *priv = (drm_file_t *) DRM(find_file_by_proc)(dev, p); \
if (!priv) { \
@@ -173,12 +199,25 @@
#define DRM_HZ hz
-#define DRM_WAIT_ON( ret, queue, timeout, condition ) \
-while (!condition) { \
- ret = tsleep( &(queue), PCATCH, "drmwtq", (timeout) ); \
- if ( ret ) \
- return ret; \
+#if defined(__FreeBSD__) && __FreeBSD_version > 500000
+#define DRM_WAIT_ON( ret, queue, timeout, condition ) \
+for ( ret = 0 ; !ret && !(condition) ; ) { \
+ mtx_lock(&dev->irq_lock); \
+ if (!(condition)) \
+ ret = msleep(&(queue), &dev->irq_lock, \
+ PCATCH, "drmwtq", (timeout)); \
+ mtx_unlock(&dev->irq_lock); \
+}
+#else
+#define DRM_WAIT_ON( ret, queue, timeout, condition ) \
+for ( ret = 0 ; !ret && !(condition) ; ) { \
+ int s = spldrm(); \
+ if (!(condition)) \
+ ret = tsleep( &(queue), PCATCH, \
+ "drmwtq", (timeout) ); \
+ splx(s); \
}
+#endif
#define DRM_WAKEUP( queue ) wakeup( queue )
#define DRM_WAKEUP_INT( queue ) wakeup( queue )
@@ -204,13 +243,28 @@
(!useracc((caddr_t)uaddr, size, VM_PROT_READ))
#define DRM_COPY_FROM_USER_UNCHECKED(arg1, arg2, arg3) \
copyin(arg2, arg1, arg3)
+#define DRM_COPY_TO_USER_UNCHECKED(arg1, arg2, arg3) \
+ copyout(arg2, arg1, arg3)
#define DRM_GET_USER_UNCHECKED(val, uaddr) \
((val) = fuword(uaddr), 0)
+#define DRM_PUT_USER_UNCHECKED(uaddr, val) \
+ suword(uaddr, val)
-#define DRM_WRITEMEMORYBARRIER( map ) \
- bus_space_barrier((map)->iot, (map)->ioh, 0, (map)->size, 0);
-#define DRM_READMEMORYBARRIER( map ) \
- bus_space_barrier((map)->iot, (map)->ioh, 0, (map)->size, BUS_SPACE_BARRIER_READ);
+/* DRM_READMEMORYBARRIER() prevents reordering of reads.
+ * DRM_WRITEMEMORYBARRIER() prevents reordering of writes.
+ * DRM_MEMORYBARRIER() prevents reordering of reads and writes.
+ */
+#if defined(__i386__)
+#define DRM_READMEMORYBARRIER() __asm __volatile( \
+ "lock; addl $0,0(%%esp)" : : : "memory");
+#define DRM_WRITEMEMORYBARRIER() __asm __volatile("" : : : "memory");
+#define DRM_MEMORYBARRIER() __asm __volatile( \
+ "lock; addl $0,0(%%esp)" : : : "memory");
+#elif defined(__alpha__)
+#define DRM_READMEMORYBARRIER() alpha_mb();
+#define DRM_WRITEMEMORYBARRIER() alpha_wmb();
+#define DRM_MEMORYBARRIER() alpha_mb();
+#endif
#define PAGE_ALIGN(addr) round_page(addr)
@@ -223,6 +277,14 @@
MALLOC_DECLARE(malloctype);
#undef malloctype
+#if __FreeBSD_version >= 480000
+#define cpu_to_le32(x) htole32(x)
+#define le32_to_cpu(x) le32toh(x)
+#else
+#define cpu_to_le32(x) (x)
+#define le32_to_cpu(x) (x)
+#endif
+
typedef struct drm_chipinfo
{
int vendor;
@@ -231,8 +293,6 @@
char *name;
} drm_chipinfo_t;
-#define cpu_to_le32(x) (x) /* FIXME */
-
typedef unsigned long dma_addr_t;
typedef u_int32_t atomic_t;
typedef u_int32_t u32;
@@ -318,8 +378,6 @@
#define spldrm() spltty()
-#define memset(p, v, s) bzero(p, s)
-
/*
* Fake out the module macros for versions of FreeBSD where they don't
* exist.
@@ -336,17 +394,21 @@
/* Macros to make printf easier */
#define DRM_ERROR(fmt, arg...) \
- printf("error: " "[" DRM_NAME ":%s] *ERROR* " fmt , __func__ , ## arg)
+ printf("error: [" DRM_NAME ":pid%d:%s] *ERROR* " fmt, \
+ DRM_CURRENTPID, __func__ , ## arg)
+
#define DRM_MEM_ERROR(area, fmt, arg...) \
- printf("error: " "[" DRM_NAME ":%s:%s] *ERROR* " fmt , \
- __func__, DRM(mem_stats)[area].name , ##arg)
-#define DRM_INFO(fmt, arg...) printf("info: " "[" DRM_NAME "] " fmt , ## arg)
+ printf("error: [" DRM_NAME ":pid%d:%s:%s] *ERROR* " fmt, \
+ DRM_CURRENTPID , __func__, DRM(mem_stats)[area].name , ##arg)
+
+#define DRM_INFO(fmt, arg...) printf("info: [" DRM_NAME "] " fmt , ## arg)
#if DRM_DEBUG_CODE
-#define DRM_DEBUG(fmt, arg...) \
- do { \
- if (DRM(flags) & DRM_FLAG_DEBUG) \
- printf("[" DRM_NAME ":%s] " fmt , __func__ , ## arg); \
+#define DRM_DEBUG(fmt, arg...) \
+ do { \
+ if (DRM(flags) & DRM_FLAG_DEBUG) \
+ printf("[" DRM_NAME ":pid%d:%s] " fmt, \
+ DRM_CURRENTPID, __func__ , ## arg); \
} while (0)
#else
#define DRM_DEBUG(fmt, arg...) do { } while (0)
@@ -358,16 +420,10 @@
#define DRM_SYSCTL_HANDLER_ARGS SYSCTL_HANDLER_ARGS
#endif
-#define DRM_SYSCTL_PRINT(fmt, arg...) \
- snprintf(buf, sizeof(buf), fmt, ##arg); \
- error = SYSCTL_OUT(req, buf, strlen(buf)); \
- if (error) return error;
-
-#define DRM_SYSCTL_PRINT_RET(ret, fmt, arg...) \
- snprintf(buf, sizeof(buf), fmt, ##arg); \
- error = SYSCTL_OUT(req, buf, strlen(buf)); \
- if (error) { ret; return error; }
-
+#define DRM_SYSCTL_PRINT(fmt, arg...) \
+ snprintf(buf, sizeof(buf), fmt, ##arg); \
+ error = SYSCTL_OUT(req, buf, strlen(buf)); \
+ if (error) return error;
#define DRM_FIND_MAP(dest, o) \
do { \
@@ -399,5 +455,7 @@
extern int DRM(sysctl_init)(drm_device_t *dev);
extern int DRM(sysctl_cleanup)(drm_device_t *dev);
-/* Memory info sysctl (drm_memory.h) */
+/* Memory info sysctl (drm_memory_debug.h) */
+#ifdef DEBUG_MEMORY
extern int DRM(mem_info) DRM_SYSCTL_HANDLER_ARGS;
+#endif
Index: sys/dev/drm/mga/mga_drv.h
===================================================================
RCS file: /home/dcvs/src/sys/dev/drm/mga/mga_drv.h,v
retrieving revision 1.2
diff -u -r1.2 mga_drv.h
--- sys/dev/drm/mga/mga_drv.h 17 Jun 2003 04:28:24 -0000 1.2
+++ sys/dev/drm/mga/mga_drv.h 13 Jan 2004 19:16:11 -0000
@@ -134,7 +134,7 @@
extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv );
extern int mga_warp_init( drm_mga_private_t *dev_priv );
-#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER(dev_priv->primary)
+#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER()
#if defined(__linux__) && defined(__alpha__)
#define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle))
@@ -145,12 +145,12 @@
#define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg)))
#define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg)))
-#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(dev_priv->mmio); MGA_DEREF( reg ) = val; } while (0)
-#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(dev_priv->mmio); MGA_DEREF8( reg ) = val; } while (0)
+#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0)
+#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0)
static inline u32 _MGA_READ(u32 *addr)
{
- DRM_READMEMORYBARRIER(dev_priv->mmio);
+ DRM_MEMORYBARRIER();
return *(volatile u32 *)addr;
}
#else
Index: sys/dev/drm/r128/r128_drv.h
===================================================================
RCS file: /home/dcvs/src/sys/dev/drm/r128/r128_drv.h,v
retrieving revision 1.2
diff -u -r1.2 r128_drv.h
--- sys/dev/drm/r128/r128_drv.h 17 Jun 2003 04:28:24 -0000 1.2
+++ sys/dev/drm/r128/r128_drv.h 13 Jan 2004 19:17:42 -0000
@@ -443,7 +443,7 @@
#if defined(__powerpc__)
#define r128_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring )
#else
-#define r128_flush_write_combine() DRM_WRITEMEMORYBARRIER(dev_priv->ring_rptr)
+#define r128_flush_write_combine() DRM_MEMORYBARRIER()
#endif
Index: sys/dev/drm/radeon/radeon.h
===================================================================
RCS file: /home/dcvs/src/sys/dev/drm/radeon/radeon.h,v
retrieving revision 1.2
diff -u -r1.2 radeon.h
--- sys/dev/drm/radeon/radeon.h 17 Jun 2003 04:28:24 -0000 1.2
+++ sys/dev/drm/radeon/radeon.h 13 Jan 2004 19:06:05 -0000
@@ -124,7 +124,7 @@
if ( dev_priv->page_flipping ) { \
radeon_do_cleanup_pageflip( dev ); \
} \
- radeon_mem_release( filp, dev_priv->agp_heap ); \
+ radeon_mem_release( filp, dev_priv->gart_heap ); \
radeon_mem_release( filp, dev_priv->fb_heap ); \
} \
} while (0)
Index: sys/dev/drm/radeon/radeon_cp.c
===================================================================
RCS file: /home/dcvs/src/sys/dev/drm/radeon/radeon_cp.c,v
retrieving revision 1.4
diff -u -r1.4 radeon_cp.c
--- sys/dev/drm/radeon/radeon_cp.c 7 Aug 2003 21:16:55 -0000 1.4
+++ sys/dev/drm/radeon/radeon_cp.c 13 Jan 2004 19:05:10 -0000
@@ -858,25 +858,25 @@
/* Initialize the memory controller */
RADEON_WRITE( RADEON_MC_FB_LOCATION,
- (dev_priv->agp_vm_start - 1) & 0xffff0000 );
+ (dev_priv->gart_vm_start - 1) & 0xffff0000 );
if ( !dev_priv->is_pci ) {
RADEON_WRITE( RADEON_MC_AGP_LOCATION,
- (((dev_priv->agp_vm_start - 1 +
- dev_priv->agp_size) & 0xffff0000) |
- (dev_priv->agp_vm_start >> 16)) );
+ (((dev_priv->gart_vm_start - 1 +
+ dev_priv->gart_size) & 0xffff0000) |
+ (dev_priv->gart_vm_start >> 16)) );
}
#if __REALLY_HAVE_AGP
if ( !dev_priv->is_pci )
ring_start = (dev_priv->cp_ring->offset
- dev->agp->base
- + dev_priv->agp_vm_start);
+ + dev_priv->gart_vm_start);
else
#endif
ring_start = (dev_priv->cp_ring->offset
- dev->sg->handle
- + dev_priv->agp_vm_start);
+ + dev_priv->gart_vm_start);
RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
@@ -894,7 +894,7 @@
RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
dev_priv->ring_rptr->offset
- dev->agp->base
- + dev_priv->agp_vm_start);
+ + dev_priv->gart_vm_start);
} else
#endif
{
@@ -1094,7 +1094,7 @@
dev_priv->ring_offset = init->ring_offset;
dev_priv->ring_rptr_offset = init->ring_rptr_offset;
dev_priv->buffers_offset = init->buffers_offset;
- dev_priv->agp_textures_offset = init->agp_textures_offset;
+ dev_priv->gart_textures_offset = init->gart_textures_offset;
if(!dev_priv->sarea) {
DRM_ERROR("could not find sarea!\n");
@@ -1103,13 +1103,6 @@
return DRM_ERR(EINVAL);
}
- DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
- if(!dev_priv->fb) {
- DRM_ERROR("could not find framebuffer!\n");
- dev->dev_private = (void *)dev_priv;
- radeon_do_cleanup_cp(dev);
- return DRM_ERR(EINVAL);
- }
DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
if(!dev_priv->mmio) {
DRM_ERROR("could not find mmio region!\n");
@@ -1139,11 +1132,10 @@
return DRM_ERR(EINVAL);
}
- if ( !dev_priv->is_pci ) {
- DRM_FIND_MAP( dev_priv->agp_textures,
- init->agp_textures_offset );
- if(!dev_priv->agp_textures) {
- DRM_ERROR("could not find agp texture region!\n");
+ if ( init->gart_textures_offset ) {
+ DRM_FIND_MAP( dev_priv->gart_textures, init->gart_textures_offset );
+ if ( !dev_priv->gart_textures ) {
+ DRM_ERROR("could not find GART texture region!\n");
dev->dev_private = (void *)dev_priv;
radeon_do_cleanup_cp(dev);
return DRM_ERR(EINVAL);
@@ -1181,26 +1173,43 @@
dev_priv->buffers->handle );
}
+ dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION )
+ & 0xffff ) << 16;
+
+ dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
+ ( ( dev_priv->front_offset
+ + dev_priv->fb_location ) >> 10 ) );
+
+ dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
+ ( ( dev_priv->back_offset
+ + dev_priv->fb_location ) >> 10 ) );
+
+ dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
+ ( ( dev_priv->depth_offset
+ + dev_priv->fb_location ) >> 10 ) );
+
+
+ dev_priv->gart_size = init->gart_size;
+ dev_priv->gart_vm_start = dev_priv->fb_location
+ + RADEON_READ( RADEON_CONFIG_APER_SIZE );
- dev_priv->agp_size = init->agp_size;
- dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
#if __REALLY_HAVE_AGP
if ( !dev_priv->is_pci )
- dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
+ dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
- dev->agp->base
- + dev_priv->agp_vm_start);
+ + dev_priv->gart_vm_start);
else
#endif
- dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
+ dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
- dev->sg->handle
- + dev_priv->agp_vm_start);
+ + dev_priv->gart_vm_start);
- DRM_DEBUG( "dev_priv->agp_size %d\n",
- dev_priv->agp_size );
- DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
- dev_priv->agp_vm_start );
- DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
- dev_priv->agp_buffers_offset );
+ DRM_DEBUG( "dev_priv->gart_size %d\n",
+ dev_priv->gart_size );
+ DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
+ dev_priv->gart_vm_start );
+ DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
+ dev_priv->gart_buffers_offset );
dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
@@ -1234,9 +1243,9 @@
/* set address range for PCI address translate
*/
- RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
- RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
- + dev_priv->agp_size - 1);
+ RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
+ RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
+ + dev_priv->gart_size - 1);
/* Turn off AGP aperture -- is this required for PCIGART?
*/
@@ -1407,7 +1416,7 @@
RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
/* Free memory heap structures */
- radeon_mem_takedown( &(dev_priv->agp_heap) );
+ radeon_mem_takedown( &(dev_priv->gart_heap) );
radeon_mem_takedown( &(dev_priv->fb_heap) );
/* deallocate kernel resources */
Index: sys/dev/drm/radeon/radeon_drm.h
===================================================================
RCS file: /home/dcvs/src/sys/dev/drm/radeon/radeon_drm.h,v
retrieving revision 1.2
diff -u -r1.2 radeon_drm.h
--- sys/dev/drm/radeon/radeon_drm.h 17 Jun 2003 04:28:24 -0000 1.2
+++ sys/dev/drm/radeon/radeon_drm.h 13 Jan 2004 18:52:42 -0000
@@ -214,11 +214,11 @@
#define RADEON_NR_SAREA_CLIPRECTS 12
-/* There are 2 heaps (local/AGP). Each region within a heap is a
+/* There are 2 heaps (local/GART). Each region within a heap is a
* minimum of 64k, and there are at most 64 of them per heap.
*/
#define RADEON_LOCAL_TEX_HEAP 0
-#define RADEON_AGP_TEX_HEAP 1
+#define RADEON_GART_TEX_HEAP 1
#define RADEON_NR_TEX_HEAPS 2
#define RADEON_NR_TEX_REGIONS 64
#define RADEON_LOG_TEX_GRANULARITY 16
@@ -404,7 +404,7 @@
unsigned long sarea_priv_offset;
int is_pci;
int cp_mode;
- int agp_size;
+ int gart_size;
int ring_size;
int usec_timeout;
@@ -419,7 +419,7 @@
unsigned long ring_offset;
unsigned long ring_rptr_offset;
unsigned long buffers_offset;
- unsigned long agp_textures_offset;
+ unsigned long gart_textures_offset;
} drm_radeon_init_t;
typedef struct drm_radeon_cp_stop {
@@ -529,16 +529,19 @@
/* 1.3: An ioctl to get parameters that aren't available to the 3d
* client any other way.
*/
-#define RADEON_PARAM_AGP_BUFFER_OFFSET 1 /* card offset of 1st agp buffer */
+#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
#define RADEON_PARAM_LAST_FRAME 2
#define RADEON_PARAM_LAST_DISPATCH 3
#define RADEON_PARAM_LAST_CLEAR 4
+/* Added with DRM version 1.6. */
#define RADEON_PARAM_IRQ_NR 5
-#define RADEON_PARAM_AGP_BASE 6 /* card offset of agp base */
+#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
+/* Added with DRM version 1.8. */
#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
#define RADEON_PARAM_STATUS_HANDLE 8
#define RADEON_PARAM_SAREA_HANDLE 9
-#define RADEON_PARAM_AGP_TEX_HANDLE 10
+#define RADEON_PARAM_GART_TEX_HANDLE 10
+#define RADEON_PARAM_SCRATCH_OFFSET 11
typedef struct drm_radeon_getparam {
int param;
@@ -547,14 +550,14 @@
/* 1.6: Set up a memory manager for regions of shared memory:
*/
-#define RADEON_MEM_REGION_AGP 1
+#define RADEON_MEM_REGION_GART 1
#define RADEON_MEM_REGION_FB 2
typedef struct drm_radeon_mem_alloc {
int region;
int alignment;
int size;
- int *region_offset; /* offset from start of fb or agp */
+ int *region_offset; /* offset from start of fb or GART */
} drm_radeon_mem_alloc_t;
typedef struct drm_radeon_mem_free {
Index: sys/dev/drm/radeon/radeon_drv.h
===================================================================
RCS file: /home/dcvs/src/sys/dev/drm/radeon/radeon_drv.h,v
retrieving revision 1.2
diff -u -r1.2 radeon_drv.h
--- sys/dev/drm/radeon/radeon_drv.h 17 Jun 2003 04:28:24 -0000 1.2
+++ sys/dev/drm/radeon/radeon_drv.h 13 Jan 2004 19:03:50 -0000
@@ -76,9 +76,11 @@
drm_radeon_ring_buffer_t ring;
drm_radeon_sarea_t *sarea_priv;
- int agp_size;
- u32 agp_vm_start;
- unsigned long agp_buffers_offset;
+ u32 fb_location;
+
+ int gart_size;
+ u32 gart_vm_start;
+ unsigned long gart_buffers_offset;
int cp_mode;
int cp_running;
@@ -133,17 +135,16 @@
unsigned long ring_offset;
unsigned long ring_rptr_offset;
unsigned long buffers_offset;
- unsigned long agp_textures_offset;
+ unsigned long gart_textures_offset;
drm_local_map_t *sarea;
- drm_local_map_t *fb;
drm_local_map_t *mmio;
drm_local_map_t *cp_ring;
drm_local_map_t *ring_rptr;
drm_local_map_t *buffers;
- drm_local_map_t *agp_textures;
+ drm_local_map_t *gart_textures;
- struct mem_block *agp_heap;
+ struct mem_block *gart_heap;
struct mem_block *fb_heap;
/* SW interrupt */
@@ -855,7 +856,7 @@
#define COMMIT_RING() do { \
/* Flush writes to ring */ \
- DRM_READMEMORYBARRIER( dev_priv->mmio ); \
+ DRM_MEMORYBARRIER(); \
GET_RING_HEAD( dev_priv ); \
RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
/* read from PCI bus to ensure correct posting */ \
Index: sys/dev/drm/radeon/radeon_mem.c
===================================================================
RCS file: /home/dcvs/src/sys/dev/drm/radeon/radeon_mem.c,v
retrieving revision 1.3
diff -u -r1.3 radeon_mem.c
--- sys/dev/drm/radeon/radeon_mem.c 7 Aug 2003 21:16:55 -0000 1.3
+++ sys/dev/drm/radeon/radeon_mem.c 13 Jan 2004 19:06:44 -0000
@@ -215,8 +215,8 @@
int region )
{
switch( region ) {
- case RADEON_MEM_REGION_AGP:
- return &dev_priv->agp_heap;
+ case RADEON_MEM_REGION_GART:
+ return &dev_priv->gart_heap;
case RADEON_MEM_REGION_FB:
return &dev_priv->fb_heap;
default:
Index: sys/dev/drm/radeon/radeon_state.c
===================================================================
RCS file: /home/dcvs/src/sys/dev/drm/radeon/radeon_state.c,v
retrieving revision 1.3
diff -u -r1.3 radeon_state.c
--- sys/dev/drm/radeon/radeon_state.c 7 Aug 2003 21:16:55 -0000 1.3
+++ sys/dev/drm/radeon/radeon_state.c 13 Jan 2004 19:08:00 -0000
@@ -895,7 +895,7 @@
{
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_clip_rect_t box;
- int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start;
+ int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
int numverts = (int)prim->numverts;
int i = 0;
RING_LOCALS;
@@ -969,7 +969,7 @@
buf->idx, start, end );
if ( start != end ) {
- int offset = (dev_priv->agp_buffers_offset
+ int offset = (dev_priv->gart_buffers_offset
+ buf->offset + start);
int dwords = (end - start + 3) / sizeof(u32);
@@ -1004,7 +1004,7 @@
{
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_clip_rect_t box;
- int offset = dev_priv->agp_buffers_offset + prim->offset;
+ int offset = dev_priv->gart_buffers_offset + prim->offset;
u32 *data;
int dwords;
int i = 0;
@@ -2174,8 +2174,8 @@
DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
switch( param.param ) {
- case RADEON_PARAM_AGP_BUFFER_OFFSET:
- value = dev_priv->agp_buffers_offset;
+ case RADEON_PARAM_GART_BUFFER_OFFSET:
+ value = dev_priv->gart_buffers_offset;
break;
case RADEON_PARAM_LAST_FRAME:
dev_priv->stats.last_frame_reads++;
@@ -2191,8 +2191,8 @@
case RADEON_PARAM_IRQ_NR:
value = dev->irq;
break;
- case RADEON_PARAM_AGP_BASE:
- value = dev_priv->agp_vm_start;
+ case RADEON_PARAM_GART_BASE:
+ value = dev_priv->gart_vm_start;
break;
case RADEON_PARAM_REGISTER_HANDLE:
value = dev_priv->mmio_offset;
@@ -2204,8 +2204,8 @@
/* The lock is the first dword in the sarea. */
value = (int)dev->lock.hw_lock;
break;
- case RADEON_PARAM_AGP_TEX_HANDLE:
- value = dev_priv->agp_textures_offset;
+ case RADEON_PARAM_GART_TEX_HANDLE:
+ value = dev_priv->gart_textures_offset;
break;
default:
return DRM_ERR(EINVAL);
@@ -2218,3 +2218,33 @@
return 0;
}
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