DragonFly submit List (threaded) for 2003-12
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AGP Updates
This patch adds a bunch of stuff from FreeBSD5. It consistantly makes
vendor specific drivers depend on agp, consistantly checks the gart size
!= 0, changes agp_generic_enable to the FreeBSD5 function, initializing
the device as v2 or v3 accordingly, syncs up agpio.h, and adds a couple
PCI Ids from FreeBSD5.
WARNING !!!!
This has only been tested on the Intel 855 Chipset. Please test this on
more hardware before commiting, especially chipsets that were added.
Thanks
-Craig
--
------------------------------------------------------------------------
Craig Dooley craig@xxxxxxxxxx
------------------------------------------------------------------------
Index: share/man/man4/agp.4
===================================================================
RCS file: /usr/srcs/dcvs/src/share/man/man4/agp.4,v
retrieving revision 1.2
diff -u -r1.2 agp.4
--- share/man/man4/agp.4 17 Jun 2003 04:36:58 -0000 1.2
+++ share/man/man4/agp.4 8 Dec 2003 06:16:16 -0000
@@ -42,16 +42,21 @@
.It
Ali M1541 host-to-AGP bridge
.It
-.\" 761 not in -stable
-AMD 751 host-to-AGP bridge
+AMD 751, 761, 762 host-to-AGP bridge
.It
-Intel i820, i840, i845, i850, and i860 host-to-AGP bridge
+Intel 440 LX, 440 BX, 440 GX, i815, and i820 host-to-AGP bridge
.It
-Intel i810, i810-DC100, i810E, and i815 SVGA controllers
+Intel i830, i840, i845, i850, and i855 host-to-AGP bridge
.It
-Intel 82443GX host-to-AGP bridge
+Intel i860, i865, and i875 host-to-AGP bridge
.It
-SiS 5591 host-to-AGP bridge
+Intel i810, i810-DC100, i810E, i815, i830, and i845 SVGA controllers
+.It
+NVIDIA nForce, and nForce2 host-to-AGP bridge
+.It
+SiS 5591, and 648 host-to-AGP bridge
+.It
+Via Apollo KT133A, MVP4, VP3, MVP3, Pro 133A, and Pro host-to-AGP bridge
.El
.Pp
The most common application of
Index: sys/sys/agpio.h
===================================================================
RCS file: /usr/srcs/dcvs/src/sys/sys/agpio.h,v
retrieving revision 1.2
diff -u -r1.2 agpio.h
--- sys/sys/agpio.h 17 Jun 2003 04:28:58 -0000 1.2
+++ sys/sys/agpio.h 8 Dec 2003 04:58:31 -0000
@@ -38,22 +38,43 @@
/*
* Macros to manipulate AGP mode words.
+ *
+ * SBA = Sideband Address Port
+ * FW = Fast Writes
*/
#define AGP_MODE_GET_RQ(x) (((x) & 0xff000000U) >> 24)
+#define AGP_MODE_GET_ARQSZ(x) (((x) & 0x0000e000U) >> 13)
+#define AGP_MODE_GET_CAL(x) (((x) & 0x00001c00U) >> 10)
#define AGP_MODE_GET_SBA(x) (((x) & 0x00000200U) >> 9)
#define AGP_MODE_GET_AGP(x) (((x) & 0x00000100U) >> 8)
-#define AGP_MODE_GET_4G(x) (((x) & 0x00000020U) >> 5)
+#define AGP_MODE_GET_GART_64(x) (((x) & 0x00000080U) >> 7)
+#define AGP_MODE_GET_OVER_4G(x) (((x) & 0x00000020U) >> 5)
#define AGP_MODE_GET_FW(x) (((x) & 0x00000010U) >> 4)
+#define AGP_MODE_GET_MODE_3(x) (((x) & 0x00000008U) >> 3)
#define AGP_MODE_GET_RATE(x) ((x) & 0x00000007U)
#define AGP_MODE_SET_RQ(x,v) (((x) & ~0xff000000U) | ((v) << 24))
+#define AGP_MODE_SET_ARQSZ(x,v) (((x) & ~0x0000e000U) | ((v) << 13))
+#define AGP_MODE_SET_CAL(x,v) (((x) & ~0x00001c00U) | ((v) << 10))
#define AGP_MODE_SET_SBA(x,v) (((x) & ~0x00000200U) | ((v) << 9))
#define AGP_MODE_SET_AGP(x,v) (((x) & ~0x00000100U) | ((v) << 8))
-#define AGP_MODE_SET_4G(x,v) (((x) & ~0x00000020U) | ((v) << 5))
+#define AGP_MODE_SET_GART_64(x,v) (((x) & ~0x00000080U) | ((v) << 7))
+#define AGP_MODE_SET_OVER_4G(x,v) (((x) & ~0x00000020U) | ((v) << 5))
#define AGP_MODE_SET_FW(x,v) (((x) & ~0x00000010U) | ((v) << 4))
+#define AGP_MODE_SET_MODE_3(x,v) (((x) & ~0x00000008U) | ((v) << 3))
#define AGP_MODE_SET_RATE(x,v) (((x) & ~0x00000007U) | (v))
-#define AGP_MODE_RATE_1x 0x00000001
-#define AGP_MODE_RATE_2x 0x00000002
-#define AGP_MODE_RATE_4x 0x00000004
+#define AGP_MODE_V2_RATE_1x 0x00000001
+#define AGP_MODE_V2_RATE_2x 0x00000002
+#define AGP_MODE_V2_RATE_4x 0x00000004
+#define AGP_MODE_V3_RATE_4x 0x00000001
+#define AGP_MODE_V3_RATE_8x 0x00000002
+#define AGP_MODE_V3_RATE_RSVD 0x00000004
+
+/* XXX: Compat */
+#define AGP_MODE_GET_4G(x) AGP_MODE_GET_OVER_4G(x)
+#define AGP_MODE_SET_4G(x) AGP_MODE_SET_OVER_4G(x)
+#define AGP_MODE_RATE_1x AGP_MODE_V2_RATE_1x
+#define AGP_MODE_RATE_2x AGP_MODE_V2_RATE_2x
+#define AGP_MODE_RATE_4x AGP_MODE_V2_RATE_4x
#define AGPIOC_BASE 'A'
#define AGPIOC_INFO _IOR (AGPIOC_BASE, 0, agp_info)
Index: sys/dev/agp/agp.c
===================================================================
RCS file: /usr/srcs/dcvs/src/sys/dev/agp/agp.c,v
retrieving revision 1.7
diff -u -r1.7 agp.c
--- sys/dev/agp/agp.c 7 Aug 2003 21:16:48 -0000 1.7
+++ sys/dev/agp/agp.c 8 Dec 2003 04:54:11 -0000
@@ -177,6 +177,11 @@
"allocating GATT for aperture of size %dM\n",
apsize / (1024*1024));
+ if (entries == 0) {
+ device_printf(dev, "bad aperture size\n");
+ return NULL;
+ }
+
gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT);
if (!gatt)
return 0;
@@ -279,18 +284,83 @@
return 0;
}
-int
-agp_generic_enable(device_t dev, u_int32_t mode)
+/*
+ * This does the enable logic for v3, with the same topology
+ * restrictions as in place for v2 -- one bus, one device on the bus.
+ */
+static int
+agp_v3_enable(device_t dev, device_t mdev, u_int32_t mode)
{
- device_t mdev = agp_find_display();
u_int32_t tstatus, mstatus;
u_int32_t command;
- int rq, sba, fw, rate;;
+ int rq, sba, fw, rate, arqsz, cal;
- if (!mdev) {
- AGP_DPF("can't find display\n");
- return ENXIO;
- }
+ tstatus = pci_read_config(dev, agp_find_caps(dev) + AGP_STATUS, 4);
+ mstatus = pci_read_config(mdev, agp_find_caps(mdev) + AGP_STATUS, 4);
+
+ /* Set RQ to the min of mode, tstatus and mstatus */
+ rq = AGP_MODE_GET_RQ(mode);
+ if (AGP_MODE_GET_RQ(tstatus) < rq)
+ rq = AGP_MODE_GET_RQ(tstatus);
+ if (AGP_MODE_GET_RQ(mstatus) < rq)
+ rq = AGP_MODE_GET_RQ(mstatus);
+
+ /*
+ * ARQSZ - Set the value to the maximum one.
+ * Don't allow the mode register to override values.
+ */
+ arqsz = AGP_MODE_GET_ARQSZ(mode);
+ if (AGP_MODE_GET_ARQSZ(tstatus) > rq)
+ rq = AGP_MODE_GET_ARQSZ(tstatus);
+ if (AGP_MODE_GET_ARQSZ(mstatus) > rq)
+ rq = AGP_MODE_GET_ARQSZ(mstatus);
+
+ /* Calibration cycle - don't allow override by mode register */
+ cal = AGP_MODE_GET_CAL(tstatus);
+ if (AGP_MODE_GET_CAL(mstatus) < cal)
+ cal = AGP_MODE_GET_CAL(mstatus);
+
+ /* SBA must be supported for AGP v3. */
+ sba = 1;
+
+ /* Set FW if all three support it. */
+ fw = (AGP_MODE_GET_FW(tstatus)
+ & AGP_MODE_GET_FW(mstatus)
+ & AGP_MODE_GET_FW(mode));
+
+ /* Figure out the max rate */
+ rate = (AGP_MODE_GET_RATE(tstatus)
+ & AGP_MODE_GET_RATE(mstatus)
+ & AGP_MODE_GET_RATE(mode));
+ if (rate & AGP_MODE_V3_RATE_8x)
+ rate = AGP_MODE_V3_RATE_8x;
+ else
+ rate = AGP_MODE_V3_RATE_4x;
+ if (bootverbose)
+ device_printf(dev, "Setting AGP v3 mode %d\n", rate * 4);
+
+ pci_write_config(dev, agp_find_caps(dev) + AGP_COMMAND, 0, 4);
+
+ /* Construct the new mode word and tell the hardware */
+ command = AGP_MODE_SET_RQ(0, rq);
+ command = AGP_MODE_SET_ARQSZ(command, arqsz);
+ command = AGP_MODE_SET_CAL(command, cal);
+ command = AGP_MODE_SET_SBA(command, sba);
+ command = AGP_MODE_SET_FW(command, fw);
+ command = AGP_MODE_SET_RATE(command, rate);
+ command = AGP_MODE_SET_AGP(command, 1);
+ pci_write_config(dev, agp_find_caps(dev) + AGP_COMMAND, command, 4);
+ pci_write_config(mdev, agp_find_caps(mdev) + AGP_COMMAND, command, 4);
+
+ return 0;
+}
+
+static int
+agp_v2_enable(device_t dev, device_t mdev, u_int32_t mode)
+{
+ u_int32_t tstatus, mstatus;
+ u_int32_t command;
+ int rq, sba, fw, rate;
tstatus = pci_read_config(dev, agp_find_caps(dev) + AGP_STATUS, 4);
mstatus = pci_read_config(mdev, agp_find_caps(mdev) + AGP_STATUS, 4);
@@ -316,12 +386,14 @@
rate = (AGP_MODE_GET_RATE(tstatus)
& AGP_MODE_GET_RATE(mstatus)
& AGP_MODE_GET_RATE(mode));
- if (rate & AGP_MODE_RATE_4x)
- rate = AGP_MODE_RATE_4x;
- else if (rate & AGP_MODE_RATE_2x)
- rate = AGP_MODE_RATE_2x;
+ if (rate & AGP_MODE_V2_RATE_4x)
+ rate = AGP_MODE_V2_RATE_4x;
+ else if (rate & AGP_MODE_V2_RATE_2x)
+ rate = AGP_MODE_V2_RATE_2x;
else
- rate = AGP_MODE_RATE_1x;
+ rate = AGP_MODE_V2_RATE_1x;
+ if (bootverbose)
+ device_printf(dev, "Setting AGP v2 mode %d\n", rate);
/* Construct the new mode word and tell the hardware */
command = AGP_MODE_SET_RQ(0, rq);
@@ -333,6 +405,34 @@
pci_write_config(mdev, agp_find_caps(mdev) + AGP_COMMAND, command, 4);
return 0;
+}
+
+int
+agp_generic_enable(device_t dev, u_int32_t mode)
+{
+ device_t mdev = agp_find_display();
+ u_int32_t tstatus, mstatus;
+
+ if (!mdev) {
+ AGP_DPF("can't find display\n");
+ return ENXIO;
+ }
+
+ tstatus = pci_read_config(dev, agp_find_caps(dev) + AGP_STATUS, 4);
+ mstatus = pci_read_config(mdev, agp_find_caps(mdev) + AGP_STATUS, 4);
+
+ /*
+ * Check display and bridge for AGP v3 support. AGP v3 allows
+ * more variety in topology than v2, e.g. multiple AGP devices
+ * attached to one bridge, or multiple AGP bridges in one
+ * system. This doesn't attempt to address those situations,
+ * but should work fine for a classic single AGP slot system
+ * with AGP v3.
+ */
+ if (AGP_MODE_GET_MODE_3(tstatus) && AGP_MODE_GET_MODE_3(mstatus))
+ return (agp_v3_enable(dev, mdev, mode));
+ else
+ return (agp_v2_enable(dev, mdev, mode));
}
struct agp_memory *
Index: sys/dev/agp/agp_ali.c
===================================================================
RCS file: /usr/srcs/dcvs/src/sys/dev/agp/agp_ali.c,v
retrieving revision 1.3
diff -u -r1.3 agp_ali.c
--- sys/dev/agp/agp_ali.c 7 Aug 2003 21:16:48 -0000 1.3
+++ sys/dev/agp/agp_ali.c 8 Dec 2003 05:32:23 -0000
@@ -100,6 +100,10 @@
return error;
sc->initial_aperture = AGP_GET_APERTURE(dev);
+ if (sc->initial_aperture == 0) {
+ device_printf(dev, "bad initial aperture size, disabling\n");
+ return ENXIO;
+ }
for (;;) {
gatt = agp_alloc_gatt(dev);
@@ -263,3 +267,5 @@
static devclass_t agp_devclass;
DRIVER_MODULE(agp_ali, pci, agp_ali_driver, agp_devclass, 0, 0);
+MODULE_DEPEND(agp_ali, agp, 1, 1, 1);
+MODULE_DEPEND(agp_ali, pci, 1, 1, 1);
Index: sys/dev/agp/agp_amd.c
===================================================================
RCS file: /usr/srcs/dcvs/src/sys/dev/agp/agp_amd.c,v
retrieving revision 1.3
diff -u -r1.3 agp_amd.c
--- sys/dev/agp/agp_amd.c 7 Aug 2003 21:16:48 -0000 1.3
+++ sys/dev/agp/agp_amd.c 8 Dec 2003 06:07:57 -0000
@@ -238,6 +238,10 @@
sc->bsh = rman_get_bushandle(sc->regs);
sc->initial_aperture = AGP_GET_APERTURE(dev);
+ if (sc->initial_aperture == 0) {
+ device_printf(dev, "bad initial aperture size, disabling\n");
+ return ENXIO;
+ }
for (;;) {
gatt = agp_amd_alloc_gatt(dev);
@@ -416,3 +420,5 @@
static devclass_t agp_devclass;
DRIVER_MODULE(agp_amd, pci, agp_amd_driver, agp_devclass, 0, 0);
+MODULE_DEPEND(agp_amd, agp, 1, 1, 1);
+MODULE_DEPEND(agp_amd, pci, 1, 1, 1);
Index: sys/dev/agp/agp_i810.c
===================================================================
RCS file: /usr/srcs/dcvs/src/sys/dev/agp/agp_i810.c,v
retrieving revision 1.3
diff -u -r1.3 agp_i810.c
--- sys/dev/agp/agp_i810.c 7 Aug 2003 21:16:48 -0000 1.3
+++ sys/dev/agp/agp_i810.c 8 Dec 2003 05:31:51 -0000
@@ -239,6 +239,10 @@
sc->bsh = rman_get_bushandle(sc->regs);
sc->initial_aperture = AGP_GET_APERTURE(dev);
+ if (sc->initial_aperture == 0) {
+ device_printf(dev, "bad initial aperture size, disabling\n");
+ return ENXIO;
+ }
gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT);
if (!gatt) {
@@ -629,3 +633,5 @@
static devclass_t agp_devclass;
DRIVER_MODULE(agp_i810, pci, agp_i810_driver, agp_devclass, 0, 0);
+MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
+MODULE_DEPEND(agp_i810, pci, 1, 1, 1);
Index: sys/dev/agp/agp_intel.c
===================================================================
RCS file: /usr/srcs/dcvs/src/sys/dev/agp/agp_intel.c,v
retrieving revision 1.3
diff -u -r1.3 agp_intel.c
--- sys/dev/agp/agp_intel.c 7 Aug 2003 21:16:48 -0000 1.3
+++ sys/dev/agp/agp_intel.c 8 Dec 2003 06:11:39 -0000
@@ -98,11 +98,17 @@
case 0x25308086:
return ("Intel 82850 host to AGP bridge");
+ case 0x33408086:
+ return ("Intel 82855 host to AGP bridge");
+
case 0x25318086:
return ("Intel 82860 host to AGP bridge");
case 0x25708086:
return ("Intel 82865 host to AGP bridge");
+
+ case 0x25788086:
+ return ("Intel 82875P host to AGP bridge");
};
if (pci_get_vendor(dev) == 0x8086)
@@ -146,6 +152,10 @@
MAX_APSIZE;
pci_write_config(dev, AGP_INTEL_APSIZE, value, 1);
sc->initial_aperture = AGP_GET_APERTURE(dev);
+ if (sc->initial_aperture == 0) {
+ device_printf(dev, "bad initial aperture size, disabling\n");
+ return ENXIO;
+ }
for (;;) {
gatt = agp_alloc_gatt(dev);
@@ -201,7 +211,9 @@
break;
case 0x1a308086: /* i845 */
+ case 0x33408086: /* i855 */
case 0x25708086: /* i865 */
+ case 0x25788086: /* i875P */
pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
| (1 << 1)), 1);
@@ -222,8 +234,10 @@
case 0x25018086: /* i820 */
case 0x1a308086: /* i845 */
case 0x25308086: /* i850 */
+ case 0x33408086: /* i855 */
case 0x25318086: /* i860 */
case 0x25708086: /* i865 */
+ case 0x25788086: /* i875P */
pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
break;
@@ -266,7 +280,9 @@
& ~(1 << 1)), 1);
case 0x1a308086: /* i845 */
+ case 0x33408086: /* i855 */
case 0x25708086: /* i865 */
+ case 0x25788086: /* i875P */
printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
& ~(1 << 1)));
@@ -396,3 +412,5 @@
static devclass_t agp_devclass;
DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, 0, 0);
+MODULE_DEPEND(agp_intel, agp, 1, 1, 1);
+MODULE_DEPEND(agp_intel, pci, 1, 1, 1);
Index: sys/dev/agp/agp_nvidia.c
===================================================================
RCS file: /usr/srcs/dcvs/src/sys/dev/agp/agp_nvidia.c,v
retrieving revision 1.1
diff -u -r1.1 agp_nvidia.c
--- sys/dev/agp/agp_nvidia.c 31 Oct 2003 21:49:23 -0000 1.1
+++ sys/dev/agp/agp_nvidia.c 8 Dec 2003 05:32:14 -0000
@@ -173,6 +173,10 @@
return (error);
sc->initial_aperture = AGP_GET_APERTURE(dev);
+ if (sc->initial_aperture == 0) {
+ device_printf(dev, "bad initial aperture size, disabling\n");
+ return ENXIO;
+ }
for (;;) {
gatt = agp_alloc_gatt(dev);
Index: sys/dev/agp/agp_sis.c
===================================================================
RCS file: /usr/srcs/dcvs/src/sys/dev/agp/agp_sis.c,v
retrieving revision 1.3
diff -u -r1.3 agp_sis.c
--- sys/dev/agp/agp_sis.c 7 Aug 2003 21:16:48 -0000 1.3
+++ sys/dev/agp/agp_sis.c 8 Dec 2003 06:12:53 -0000
@@ -65,6 +65,8 @@
switch (pci_get_devid(dev)) {
case 0x00011039:
return ("SiS 5591 host to AGP bridge");
+ case 0x06481039:
+ return ("SiS 648 host to AGP bridge");
};
if (pci_get_vendor(dev) == 0x1039)
@@ -100,6 +102,10 @@
return error;
sc->initial_aperture = AGP_GET_APERTURE(dev);
+ if (sc->initial_aperture == 0) {
+ device_printf(dev, "bad initial aperture size, disabling\n");
+ return ENXIO;
+ }
for (;;) {
gatt = agp_alloc_gatt(dev);
@@ -255,3 +261,5 @@
static devclass_t agp_devclass;
DRIVER_MODULE(agp_sis, pci, agp_sis_driver, agp_devclass, 0, 0);
+MODULE_DEPEND(agp_sis, agp, 1, 1, 1);
+MODULE_DEPEND(agp_sis, pci, 1, 1, 1);
Index: sys/dev/agp/agp_via.c
===================================================================
RCS file: /usr/srcs/dcvs/src/sys/dev/agp/agp_via.c,v
retrieving revision 1.3
diff -u -r1.3 agp_via.c
--- sys/dev/agp/agp_via.c 7 Aug 2003 21:16:48 -0000 1.3
+++ sys/dev/agp/agp_via.c 8 Dec 2003 05:32:22 -0000
@@ -63,16 +63,18 @@
return NULL;
switch (pci_get_devid(dev)) {
+ case 0x03051106:
+ return ("VIA 82C8363 (Apollo KT133A) host to PCI bridge");
case 0x05011106:
return ("VIA 8501 (Apollo MVP4) host to PCI bridge");
case 0x05971106:
return ("VIA 82C597 (Apollo VP3) host to PCI bridge");
case 0x05981106:
return ("VIA 82C598 (Apollo MVP3) host to PCI bridge");
+ case 0x06051106:
+ return ("VIA 82C694X (Apollo Pro 133A) host to PCI bridge");
case 0x06911106:
return ("VIA 82C691 (Apollo Pro) host to PCI bridge");
- case 0x03051106:
- return ("VIA 82C8363 (Apollo KT133A) host to PCI bridge");
};
if (pci_get_vendor(dev) == 0x1106)
@@ -108,6 +110,10 @@
return error;
sc->initial_aperture = AGP_GET_APERTURE(dev);
+ if (sc->initial_aperture == 0) {
+ device_printf(dev, "bad initial aperture size, disabling\n");
+ return ENXIO;
+ }
for (;;) {
gatt = agp_alloc_gatt(dev);
@@ -254,3 +260,5 @@
static devclass_t agp_devclass;
DRIVER_MODULE(agp_via, pci, agp_via_driver, agp_devclass, 0, 0);
+MODULE_DEPEND(agp_via, agp, 1, 1, 1);
+MODULE_DEPEND(agp_via, pci, 1, 1, 1);
Index: sys/dev/agp/agpreg.h
===================================================================
RCS file: /usr/srcs/dcvs/src/sys/dev/agp/agpreg.h,v
retrieving revision 1.3
diff -u -r1.3 agpreg.h
--- sys/dev/agp/agpreg.h 31 Oct 2003 21:49:23 -0000 1.3
+++ sys/dev/agp/agpreg.h 6 Dec 2003 03:59:15 -0000
@@ -178,6 +178,32 @@
#define AGP_I830_GCC1_GMASIZE_128 0x00
/*
+ * Config registers for 852GM/855GM/865G device 0
+ */
+#define AGP_I855_GCC1 0x52
+#define AGP_I855_GCC1_DEV2 0x08
+#define AGP_I855_GCC1_DEV2_ENABLED 0x00
+#define AGP_I855_GCC1_DEV2_DISABLED 0x08
+#define AGP_I855_GCC1_GMS 0x70
+#define AGP_I855_GCC1_GMS_STOLEN_0M 0x00
+#define AGP_I855_GCC1_GMS_STOLEN_1M 0x10
+#define AGP_I855_GCC1_GMS_STOLEN_4M 0x20
+#define AGP_I855_GCC1_GMS_STOLEN_8M 0x30
+#define AGP_I855_GCC1_GMS_STOLEN_16M 0x40
+#define AGP_I855_GCC1_GMS_STOLEN_32M 0x50
+
+/*
+ * 852GM/855GM variant identification
+ */
+#define AGP_I85X_CAPID 0x44
+#define AGP_I85X_VARIANT_MASK 0x7
+#define AGP_I85X_VARIANT_SHIFT 5
+#define AGP_I855_GME 0x0
+#define AGP_I855_GM 0x4
+#define AGP_I852_GME 0x2
+#define AGP_I852_GM 0x5
+
+/*
* NVIDIA nForce/nForce2 registers
*/
#define AGP_NVIDIA_0_APBASE 0x10
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