Re: GSoC: Add SMT/HT awareness to DragonFlyBSD scheduler

[Mihai Carabas <mihai.carabas@xxxxxxxxx>]

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Hi,


> Is this correct?
>
> e.g.: CHIP0 has cores 0,1,2,8,9,10 and so does CHIP1,
>   but there is no core labelled 3,4,5,6,7 and 11
> also the cpu numbering seems 'staggered' to me -
>   e.g. chip0/core0/{cpu1,cpu13) and chip1/core0/{cpu0,cpu12}
> rather than something more like:
>   chip0/core0-5/cpu0-11 & chip1/core6-11/cpu12-23
>
There is no standard on how the cpu's are numbered. The cpu1-cpu13,
cpu0-cpu12,etc grouping of HT threads is ok because I tested the HT passive
scheduling (the first part of my project) and it seems to give good
results. The core numbers are extracted from the APICIDs (the core_bits and
logical_bits are ok). We dumped the APICIDs with acpidump and they are ok.
I haven't look much at this issue.

Mihai

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<div class=3D"gmail_quote"><div>Hi,</div><div>=A0</div><blockquote class=3D=
"gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;padding=
-left:1ex">Is this correct?<br>
<br>
e.g.: CHIP0 has cores 0,1,2,8,9,10 and so does CHIP1,<br>
=A0 but there is no core labelled 3,4,5,6,7 and 11<br>
also the cpu numbering seems &#39;staggered&#39; to me -<br>
=A0 e.g. chip0/core0/{cpu1,cpu13) and chip1/core0/{cpu0,cpu12}<br>
rather than something more like:<br>
=A0 chip0/core0-5/cpu0-11 &amp; chip1/core6-11/cpu12-23<br></blockquote><di=
v>There is no standard on how the cpu&#39;s are numbered. The cpu1-cpu13, c=
pu0-cpu12,etc grouping of HT threads is ok because I tested the HT passive =
scheduling (the first part of my project) and it seems to give good results=
. The core numbers are extracted from the APICIDs (the core_bits and logica=
l_bits are ok). We dumped the APICIDs with acpidump and they are ok. I have=
n&#39;t look much at this issue.</div>
<div><br></div><div>Mihai</div></div>

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