Re: GSoC: Add SMT/HT awareness to DragonFlyBSD scheduler

[Mihai Carabas <mihai.carabas@xxxxxxxxx>]

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Hi Matt,

On Wed, Jun 27, 2012 at 4:41 AM, Matt Emmerton <matt@gsicomp.on.ca> wrote:

> Mihai,****
>
> ** **
>
> This is great stuff.****
>
> ** **
>
> For the CPU topology option, are cbits/lbits values considered a mask (eg,
> reserve N bits for core ID or thread ID), or are they the log2 of the
> threads/core or cores/package that you want to simulate?  If it's the
> latter, then I envision problems attempting to simulate systems that don't
> follow strict power-of-2 scaling (such as the AMD Phenom X6 that I'm
> writing this on, with 6 cores/package.)
>

Those are the number of bits within the APICID, from where you can get the
core ID and the thread ID. For each available CPU, these IDs are compared
to BSD ID (the cpu0 which does the init). Based on this, the cpu topology
is discovered. Because is a virtual environment and there is no APICID (the
APICID = CPUID basicly), yes you cannot simulate an AMD Phenom X6 (the
cpuid's are consecutive). But I'm curious if the real code works on your
Phenom X6. Could you compile my repo and then issue a sysctl
kern.cpu_topology?

Thank you,
Mihai

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Hi Matt,<br><br><div class=3D"gmail_quote">On Wed, Jun 27, 2012 at 4:41 AM,=
 Matt Emmerton <span dir=3D"ltr">&lt;<a href=3D"mailto:matt@gsicomp.on.ca"; =
target=3D"_blank">matt@gsicomp.on.ca</a>&gt;</span> wrote:<br><blockquote c=
lass=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;=
padding-left:1ex">
<div lang=3D"EN-US" link=3D"blue" vlink=3D"purple"><p class=3D"MsoNormal"><=
span style=3D"font-size:11.0pt;font-family:&quot;Calibri&quot;,&quot;sans-s=
erif&quot;;color:#1f497d">Mihai,<u></u><u></u></span></p><p class=3D"MsoNor=
mal"><span style=3D"font-size:11.0pt;font-family:&quot;Calibri&quot;,&quot;=
sans-serif&quot;;color:#1f497d"><u></u>=A0<u></u></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt;font-family:&quot;Ca=
libri&quot;,&quot;sans-serif&quot;;color:#1f497d">This is great stuff.<u></=
u><u></u></span></p><p class=3D"MsoNormal"><span style=3D"font-size:11.0pt;=
font-family:&quot;Calibri&quot;,&quot;sans-serif&quot;;color:#1f497d"><u></=
u>=A0<u></u></span></p>
<p class=3D"MsoNormal"><span style=3D"font-size:11.0pt;font-family:&quot;Ca=
libri&quot;,&quot;sans-serif&quot;;color:#1f497d">For the CPU topology opti=
on, are cbits/lbits values considered a mask (eg, reserve N bits for core I=
D or thread ID), or are they the log2 of the threads/core or cores/package =
that you want to simulate?=A0 If it&#39;s the latter, then I envision probl=
ems attempting to simulate systems that don&#39;t follow strict power-of-2 =
scaling (such as the AMD Phenom X6 that I&#39;m writing this on, with 6 cor=
es/package.)</span></p>
</div></blockquote><div>=A0</div><div style=3D"color:rgb(34,34,34);font-fam=
ily:arial,sans-serif;font-size:13px;background-color:rgb(255,255,255)">Thos=
e are the number of bits within the APICID, from where you can get the core=
 ID and the thread ID. For each available CPU, these IDs are compared to BS=
D ID (the cpu0 which does the init). Based on this, the cpu topology is dis=
covered. Because is a virtual environment and there is no APICID (the APICI=
D =3D CPUID basicly), yes you cannot simulate an AMD Phenom X6 (the cpuid&#=
39;s are consecutive). But I&#39;m curious if the real code works on your P=
henom X6. Could you compile my repo and then issue a sysctl kern.cpu_topolo=
gy?</div>
<div style=3D"color:rgb(34,34,34);font-family:arial,sans-serif;font-size:13=
px;background-color:rgb(255,255,255)"><br></div><div style=3D"color:rgb(34,=
34,34);font-family:arial,sans-serif;font-size:13px;background-color:rgb(255=
,255,255)">
Thank you,</div><div><span style=3D"background-color:rgb(255,255,255);color=
:rgb(34,34,34);font-family:arial,sans-serif;font-size:13px">Mihai</span></d=
iv></div>

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