DragonFly kernel List (threaded) for 2007-07
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DragonFly kernel List (threaded) for 2007-07
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fc5cdc4k2df92b2d5c109dab@mail.gmail.com> <4699588C.6040005@fs.ei.tum.de> <46995FB0.1080108@netphreax.net> <46996887.10404@fs.ei.tum.de> <200707150029.l6F0TQup002271@apollo.backplane.com>
From: "Simon 'corecode' Schubert" <corecode@fs.ei.tum.de>
Subject: Re: 4mb PAGES for mbuf clusters
Date: Sun, 15 Jul 2007 02:39:26 +0200
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Matthew Dillon wrote:
> :
> :Thomas E. Spanjaard wrote:
> :>>> Is not the large pages necessary for 64 GB memory support ?
> :>> no.  and PAE is stupid, so we won't do that.  it's really stupid.  
> :> Actually, we will do that. Perhaps not on x86-32, but it sure is a 
> :> requirement for 64bit long mode on x86-64...
> :what is?  PAE is not, just the 4-level page table.
>      Nothing wrong with the 4-level page table.  It's designed so you
>      can assign address spaces their own independant page table directories.
>      So, for example, the kernel would no longer need to stuff all the
>      kernel's PTEs into each user page table in order to keep the kernel
>      mapped.

yah, and you simply need it to address more than 4GB.

>      Besides, pretty much all the levels except the last are cached.

but they will be flushed on a task switch, right?  We should check out that GLOBAL PTE flag which prevents TLB entries to be flushed.

cheers
  simon

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