Re: SMP CPU Synchronization patch - needs testing on SMP systems

[Pete Carah <pete@xxxxxxxxxxxx>]

OK - I just did the patch and made a kernel on my smp system
(supermicro, 2x1g P3, via chipset).  It's currently gen'd without
invariants (or indeed any of the debugging options except for ddb alone...)
If it gets in trouble I can fix that :-)
At least it boots.  Just trying a -j4 buildworld.

In case it matters, the first cpuid looks like:
CPU: Intel Pentium III (999.53-MHz 686-class CPU)
  Origin = "GenuineIntel"  Id = 0x68a  Stepping = 10
  Features=0x383fbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CM
OV,PAT,PSE36,MMX,FXSR,SSE>
I don't know the significance of stepping 10 but hopefully those with the
Intel errata docs do.  Also I hope the via chipset isn't too much problem; I
remember several screwups in the past with via southbridges (like silent
data corruption writing to disk :-(.

I'll try exercise it in the next few days.  It does occasionally die
(usually just locks up so no panic or ddb output, also it's remote
and a bit hard to get to for debugging).

Currently I have 3 dragonfly systems going; I was going to move a few
more over to this but got bit by the missing ufs2 support so have to wait
till that shows up or I get frustrated enough to attempt to port it
(probably a bit much to bite off but I've done worse in my past.)

-- Pete